1. Field
Exemplary embodiments relate to a memory device. Particularly, exemplary embodiments relate to a precharge circuit for precharging a bit line and a bit line bar of a memory element, a memory device including a memory element such as an SRAM cell which is precharged by the precharge circuit, and an SRAM global counter embodied using SRAM cells which are precharged by the precharge circuit.
2. Discussion of the Related Art
Generally, in a memory device such as, e.g., a CMOS image sensor (CIS), a counter counts image data for one row time, converts the image data into a digital code, and transfers the digital code to a digital block of a subsequent stage.
A counter may largely fall into a local counter and a global counter. In general, a CMOS image sensor has been embodied mainly by using the local counter. However, a growing number of CMOS image sensors are being developed or being mass-produced by using the global counter. This is because the global counter provides advantages such as reduced power and area so that the quality of CMOS image sensor using it can be improved, in comparison with the local counter. In particular, by using an SRAM global counter which uses SRAM cells, the area can be further reduced.
When it comes to the SRAM global counter, however, issues may arise because the stored value in an SRAM cell tends to change at a high voltage, while a sense amplifier does not properly sense data values at a low voltage. These issues are observed regardless of the characteristics of transistors that vary.
In this regard, background descriptions are made below as to the phenomenon that the stored value in an SRAM cell changes due to the structural limitation of the SRAM cell and a corner change when a high voltage is supplied to both ends of the SRAM cell. Both ends of the SRAM cell mean a bit line and a bit line bar.
The basic operation principle of an SRAM cell is as follows: a write operation is performed by applying predetermined voltage values as both ends' voltages, whereas in a read operation, after applying a power supply voltage VDD as both ends' voltages, the magnitude of either one of the both ends' voltages is changed according to the value stored in the SRAM cell to induce a voltage difference between the both ends' voltages, and then a sense amplifier senses the difference between both ends' voltages.
In this regard, when performing the operation of reading a value stored in the SRAM cell, if the both ends' voltages and the loading capacitance are substantially large, a problem is caused in that the SRAM cell may not change the magnitude of either one of both ends' voltages, and rather the internally stored value may change by both ends' voltages. In order to address this problem, an SNM (static noise margin, which is a margin for preventing the stored value of an SRAM cell from changing) is taken into consideration in designing an SRAM cell.
Nonetheless, when it comes to an SRAM cell used in an SRAM global counter of a CMOS image sensor (CIS), the loading capacitance is very large, which is equivalent to a power supply voltage VDD being applied, and therefore the stored value of the SRAM cell tends to be distorted frequently. In particular, the distortion phenomenon occurs more often at a fast-slow (FS) corner (where the letter F refers to the characteristic of an NMOS transistor and the letter S refers to the characteristic of a PMOS transistor). Due to the nature of a CMOS image sensor (CIS), an error in only one SRAM cell would even cause the entire chip to become a defective product, which will adversely affect the yield of the CIS chips.
On the other hand, in the case of reading the stored value of an SRAM cell, there are largely two time periods within one cycle. The first time as a precharge period corresponds to an operation of initializing the voltages of a bit line and a bit line bar with a power supply voltage VDD before the SRAM cell is turned on. The second time as a sensing period corresponds to an operation in which the SRAM cell is actually turned on, and the node voltage of one of the bit line and the bit line bar is dropped to induce a difference between both ends' voltages, which a sense amplifier reads out.
If the precharge period is too short or the sensing period is too short, the probability of an error that the sense amplifier does not sense the stored value of the SRAM cell increases. Conversely, if the precharge period is too long, the probability of an error that the stored value of the SRAM cell changes increases.
Describing this in more detail, if a sensing time is short, since the difference between the both ends' voltages would not be sufficient, the possibility of the sense amplifier not being able to sense the value of the difference exists. Therefore, although the sensing time should be sufficient, it would lead to a decrease in the precharge time with the time of one cycle being fixed and the operating speed increasing. If the precharge time decreases, it will also negatively affect the sensing performance of the sense amplifier because the precharge would not be performed.
In addition, as the number of SRAM cells increases in a high pixel product, the loading capacitance inevitably increases, and the lengths of the precharge time and the sensing time transferred to the SRAM cells vary depending on their positions, resulting in more difficulties for a stable operation.